This invention relates to a digital bridge circuit which intercouples two completely different busses together; and more particularly, it relates to a novel structure for a digital bridge circuit by which a high operating speed is achieved without deadlocks.
In the prior art, it is common practice to provide some type of bus to which a variety of data processing units can be connected and over which those data processing units can send data to each other. Two examples of such busses are the SCSI bus and the EISA bus. These busses are industry standards; and a complete specification of the SCSI bus and the EISA bus are publicly available. A copy of the SCSI bus specification may be purchased from Global Engineering Documents, 2850 McGaw, Irvine, Calif. 92714; and a copy of the EISA bus specification may be purchased from BCPR Services, Inc., P.O. Box 11137, Spring, Tex. 77391-1137.
Both the SCSI bus and the EISA bus include a set of data lines on which data can be sent from one unit to another. However, both the SCSI bus and the EISA bus have their own unique set of control lines and their own unique signal protocols, which are entirely different from each other. Consequently, in order for any data processing unit on the SCSI bus to send data to any another data processing unit on a EISA bus, or vice versa, a bridge circuit is required which intercouples the two busses together.
In the prior art, one such bridge circuit is described in a March, 1993 publication by PLX Technology, Inc. whose main offices are at 625 Clyde Avenue, Mountain View, Calif. 94043. This particular publication is an application note for a PLX integrated circuit chip which is designated PLX EISA 9020BV; and the publication itself is entitled, "Application Note--EISA Direct Bus Master Interface Chip for NCR 53C7X0 SCSI Processor". In that publication a circuit diagram, labeled FIG. 1, shows how the NCR 53C7X0 integrated circuit chip and PLX 9020BV integrated circuit chip may be interconnected with other support circuitry to form a bridge circuit between the EISA bus and the SCSI bus.
However, the NCR 53C7X0 integrated circuit chip is a microprocessor which sequentially reads and executes instructions during its operation; and a major drawback of the FIG. 1 bridge circuit in the above publication is that the instructions for the microprocessor are stored in a memory which must be attached to and read over the EISA bus. Thus, the reading of each instruction includes a request to use the EISA bus.
Unfortunately, an EISA bus latency time period is encountered between each request to use the EISA bus and the subsequent grant to actually use the bus. This latency time period occurs since, at any one time instant, several other data processing units will also be requesting the use of the EISA bus. Such a latency time period greatly reduces the overall performance of the bridge circuit because the instructions for the microprocessor must be read frequently.
Accordingly, a primary object of the present invention is to provide an improved structure for a bridge circuit between an EISA bus and a SCSI bus wherein a microprocessor fetches instructions with essentially no latency time.